In a system for transferring data between digital electronic devices, one of the devices is typically responsible for controlling data transfers and is designated the system controller, or master, while other devices in the system operate in conjunction with the master and are termed slaves. For expository convenience, the present invention is illustrated with reference to slaves that are I/O devices, although it will be recognized other types of slave devices may of course be used.
In most prior art systems, the system controller and the I/O devices are interconnected with a number of common buses. These buses typically include an address bus, an enable bus, a data bus, a clock bus, a read bus, a write bus, and one or more interrupt lines. Data transfer is controlled by the system controller through signals sent on these buses.
For example, when data is written from the system controller to an I/O device, the system controller is required to provide the address of the I/O device to the address bus, an enable signal to the enable bus, and a write signal to the write bus before sending data on the data bus in synchronization with a clock signal on the clock bus. The signal on the address bus serves to identify the I/O device to which the data is to be transferred. The address bus often comprises plural wires.
When reading information from an I/O device, the system controller again places the address of the device on the address bus while applying an enable signal to the enable bus and a read signal to the read bus. The system controller then reads information placed on the data bus by the addressed I/O device in synchronization with a clock signal on the clock bus.
Data transfer may also be initiated by an I/O device. When a data transfer is initiated by an I/O device, the I/O device applies an interrupt request signal to an interrupt line and the system controller services the request by determining which device generated the interrupt request and completing the requested read or write operation as described above.
One significant disadvantage of the prior art described above is the large number of wires required to connect an I/O device to the system. The I/O circuitry of an I/O device is typically realized as an integrated circuit. Each wire connected to an integrated circuit requires a separate pin and a pad on the chip. Each pad consumes a very large area of the chip compared to the area required for other discrete logic elements. Thus, each additional pad severely limits the amount of logic elements that may be placed on the chip, and consequently limits the complexity and functionality of the circuit. Also, the size of the circuit package is determined by the number of pins: the greater the number of pins, the larger the chip package. It is therefore advantageous to minimize the number of wires required to connect the I/O device to the system.
A further disadvantage results from the requirement of identifying the subject I/O device through a coded address sent on an address bus. The number of address code combinations is limited by the number of addressing pins that have been provided on the I/O circuit of the I/O device. The number of different address codes available, and hence the number of allowable I/O devices in the system, is two to the nth power, where n is the number of dedicated address pins. Many systems are therefore limited in the number of I/O devices allowed in the system by the number of address pins provided in the I/O devices.
In accordance with the present invention, a communications/control scheme is provided wherein each I/O device is connected to the system controller via three lines. One of the lines is a bidirectional enable/interrupt line connecting the I/O device to the system controller. The enable/interrupt line conveys both an enable signal to the I/O device and an interrupt request to the system controller. The remaining two wires are bussed lines that connect to all I/O devices and the system controller. One of the lines is a data bus for conveying data between the I/O devices and the system controller. The other is a clock bus for conveying a synchronizing signal for synchronizing serial data transmission. By this arrangement, a sparse control/communications network is provided that can accommodate an arbitrarily large number of I/O devices without a commensurate increase in the number of lines provided to each I/O device.
The foregoing and additional features and advantages of the present invention will be more readily apparent from the following detailed description thereof, which proceeds with reference to the accompanying drawings.